參數(shù)資料
型號: LV71081E
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 20 MM, QIP-100
文件頁數(shù): 30/31頁
文件大?。?/td> 375K
代理商: LV71081E
LV71081E
No.A1610-8/31
Block Diagram
75
Ω
75
Ω
22
μF
75
Ω
75
Ω
Tuner V_IN
AV4(Rear)R_IN
Tuner2 AR IN
GND_AL
22
μ
F
A
V3(Front)R_IN
+
75
Ω
100
μF
+
1.0
μF
1.0
μF
1.0
μF
1.0
μF
1.0
μF
1.0
μF
+
1k
Ω
10
μF
+
10
μF
+
10
μF
+
10
μF
1k
Ω
1k
Ω
1k
Ω
+
25
26
27
28
29
30
19
20
21
22
23
24
13
14
15
16
18
7
8
10
11
4
6
86
85
84
83
82
81
92
90
89
88
87
98
96
94
100
46
49
39
40
42
44
34
36
37
38
32
A
V3(Front)C_IN
V
CC
12V_A
V
CC
ALL
5V
VCR
Y_IN
VCR
C_IN
REF
4.5V
A
V4(Rear)Y_IN
TUNER2
V
IN
V
CC
5V_VC
GND_REF
A
V1(16pin)FB_OUT
EXT_CTL3
EXT_CTL4
C_SYNC_OUT
Slicer
V
CC
5V_VSW
Y/V_ADC
V_SYNC_OUT
ENC.
C_IN
V_DET_OUT
SDA_IN
SCL_IN
V_DET_IN
GND_VSW
ENC.
G/Y_IN
GND_LOGIC
ENC.
R/R-Y_IN
V
CC
_LOGIC
ENC.
Y_IN
REG
2.5
ENC.
B/B-Y_IN
56
55
54
53
52
62
61
60
59
58
57
68
67
66
65
64
63
74
73
72
71
70
69
80
79
78
77
76
75
A_DAC_R_IN
VCR_R_IN
TUNER1 AR_IN
AV2(2pin)
R_IN
AV1(2pin)
R_IN
TUNER_AL_IN
AV2(6pin)
L_IN
AV1(6pin)
L_IN
AV4(Rear)L_IN
TUNER2 AL
RV3(Front)
L_IN
REG 9V AR
N.C.
GND_REG
REG 9V AL
A_DAC_L_IN
VCR_L_IN
AV2(1pin)
R_OUT
AV2(3pin)
L_OUT
AV1(1pin)
R_OUT
AV1(3pin)
L_OUT
N.C.
A_ADC_R
A_ADC_L
N.C.
GND_AR
VCC 5V_VL
N.C.
GND_VL
AV1(19pin)
V_OUT
AV1(8pin)
FSS_OUT
AV2(19pin)
V_OUT
GND_VC
V_OUT
(Line_OUT)
EXT_CTL1
Audio_Mute_Filter
AV1(11pin)
G_OUT
GND-RGB
VCC 5V_RGB
AV1(15pin)
R/C_OUT
SYNC_SEP_LPF
AV1(7pin)
B_OUT
REG 2.5
GND_VD
AV2(7pin)
B_IN
VCC 5V_VD
0.1
μ
F
C_ADC
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
1.0
μF
1.0
μF
1.0
μF
1.0
μF
1.0
μF
1.0
μF
1.0
μF
A
V3(Front)Y_IN
A
V3(Front)V_IN
A
V2(20pin)
V/Y_IN
0.1
μF
0.1
μF
0.1
μF
AV2(15pin)
R/C_IN
0.1
μF
0.01
μF
AV2(11pin)
G_IN
0.1
μF
A
V2(16pin)FB_IN
A
V1(20pin)V_IN
0.1
μF
0.1
μF
0.1
μF
0.1
μF
0.1
μF
0.1
μF
100k
Ω
SA2R
SA18R
Mute
e
d
c
b
a
100k
Ω
100k
Ω
100k
Ω
100k
Ω
100k
Ω
100k
Ω
0.1
μF
0.1
μF
0.1
μF
1.0
μF
A
V4(Rear)V_IN
A
V4(Rear)C_IN
9
12
1
2
17
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
F
0.01
μ
F
REF
REG
Bias
Clamp
FSS
OUT
Serial
EXT
CTL4
ADC
AMP
V
-SYNC SEP
SYNC SEP
EXT
CTL3
45
47
43
SA3R
e
d
c
b
a
SA1R
Mute
e
d
c
b
a
SV2
SV17V
SV14
SV12b
SV1
Mute
e
d
c
b
a
ba
SV1
Mute
e
d
f
c
b
a
SA4R
Mute
d
c
b
a
12dB
SA2L
SA18L
Mute
e
d
c
b
a
100k
Ω
100k
Ω
100k
Ω
100k
Ω
100k
Ω
100k
Ω
100k
Ω
REG
SA3L
e
d
c
b
a
SA1L
Mute
e
d
c
b
a
Mute
a
b
c
b
f
SA4L
Mute
d
c
b
a
Mute
a
bd
f
ce
SV6
Mute
e
d
c
b
a
SV6
SV5
e
d
c
b
a
SV3
d
c
b
a
SV4
SV7
Mute
d
c
b
a
d
c
b
a
c
b
a
0V
5V
12dB
SV16
b
a
ab
Buf
51
Mute
LPF
Buf
Mute
LPF
Buf
Mute
LPF
Buf
ADC
AMP
Mute
LPF
Bias
REG1
REG
EXT
CTL1
6MHz
0dB
6dB /0dB
0dB/
-12dB
0dB/
-12dB
Bias
6dB
SV13b
Mute
a
bd
f
ce
e
6dB
SV1
1b
6dB
93
Clamp
6MHz
Clamp /Bias
6MHz
Clamp /Bias
6MHz
Clamp /Bias
6MHz
95
97
Bias
5
3
91
99
48
50
41
33
31
35
Dr
V
ideo
signal
detection
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