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參數(shù)資料
| 型號： | LX1725ILQ-TR |
| 廠商： | MICROSEMI CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 16 W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC32 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, PLASTIC, MLPQ-32 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 377K |
| 代理商： | LX1725ILQ-TR |
LX1725
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
2
Page
WWW
.Microse
m
i
.CO
M
15W+15W Stereo Class-D Amplifier
Filterless 30W Mono in BTL
Copyright
2004
Rev. 1.1, 2005-11-04
TM
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VPOS/VNEG, VPOSA/VNEGA)......................... -0.3V to
±15V or 30V
Common Supply Voltage (VCOM, VCOMA)................................. -0.3V to
±15V or 30V
Analog Supply Voltage (V5V)..........................................................................-0.3 to 7.0V
Input Voltage (IN1P, IN1M, IN2P, IN2M).......................................................-0.3 to 7.0V
Standby and Mute Voltage (STBY, MUTE).....................................................-0.3 to 7.0V
Synchronization Input Voltage (MASTER, SYNC) .........................................-0.3 to 7.0V
Operating Temperature ...............................................................................-40°C to +85°C
Maximum Operating Junction Temperature ............................................................. 150°C
Storage Temperature ................................................................................... -65°C to 150°C
Peak Package Solder Reflow Temp.(40 second maximum exposure) ......... 260°C (+0, -5)
Note: Exceeding these ratings could cause damage to the device. All voltages are with
respect to Ground. Currents are positive into, negative out of specified terminal.
TH ERMAL DATA
LQ Plastic MLPQ 32-Pin
THERMAL RESISTANCE
-JUNCTION TO CASE,
θ
JC
1.12
°C/W
THERMAL RESISTANCE
-JUNCTION TO AMBIENT,
θ
JA
15.5
°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The
θ
JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the
above assume no ambient airflow.
PACKAGE PIN OUT
1
9
17
25
VPOSA
VCOMA
SYNC
FLAG
RILIM
VREF
COSC
VNEGA
IN
2
P
IN
2
M
N.
C.
N.
C.
OU
TREF2
VNE
G
A
VGN
D
MUT
E
MASTER
VPOS2
OUT2
VNEG2
VNEG1
OUT1
VPOS1
STBY
IN1P
IN1M
N.C
.
N.C
.
OU
T
R
E
F
1
HI
G
A
IN
V5
V
VCO
M
2
3
4
5
6
7
8
10
11
12
13
14
15
16
18
19
20
21
22
23
24
26
27
28
29
30
31
32
LQ PACKAGE
(Top View)
Center Pad is VNEG
N.C. – No Internal Connection
RoHS / Pb-free 100% Matte Tin Lead Finish
FUNCTIONAL PIN DESCRIPTION
Name
Description
VPOSA
Analog voltage sense for VPOS voltage. Needs to be protected from noise at VPOS1 and VPOS2. Connect to
VPOS bus with appropriate filtering. For VPOSA – VNEGA less than 10V, the under voltage lockout circuit will
keep the part in sleep mode. Typically 250A is drawn at this pin.
VCOMA
Analog voltage sense for VCOM voltage. Typically 150A is drawn at this pin.
SYNC
Bi-directional clock signal pin. In Master mode, this pin outputs the clock to other slave units. In Slave mode,
this pin is a clock input. CMOS logic levels.
FLAG
Monitor point that indicates a fault has been detected. This pin goes high during the power on reset period, when
current limiting is in effect, when the voltage at VPOS – VNEG is less than 10V or greater than 33V, when the
V5V voltage is less than 4V, and when an over-temperature condition is detected. CMOS logic levels.
RILIM
A current limit-programming resistor should be connected between this pin and ground. A 50K
Ω resistor will give
a 3.75A current limit threshold. This pin may be connected to V5V in which case both current limiting protection
and over-voltage protection will be disabled.
VREF
2.25V reference voltage, used as a local “gnd” reference. Place a decoupling capacitor greater than 1F
between this pin and VGND. This pin will be prone to instability for capacitor values less than this. In
applications where more several LX1725s are synchronized together, the VREF pins should all be tied together
so that all units use a common VREF voltage.
COSC
Place a capacitor between this pin and VGND to generate the PWM triangle wave. A 125pF capacitor will give
an oscillation frequency of about 373KHz. In Master mode, this pin serves as the output for the triangle wave. In
Slave mode, this pin is an input. The total capacitance on this pin will determine the frequency of oscillation.
PP
AA
CC
KK
AA
GG
EE
DD
AA
TT
AA
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