參數資料
型號: LXT351
廠商: Intel Corp.
英文描述: T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
中文描述: 短途的T1/E1收發(fā)器與晶體抖動衰減
文件頁數: 37/46頁
文件大小: 1132K
代理商: LXT351
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
LXT351
Datasheet
37
Table 26. Master and Transmit Clock Timing Characteristics for T1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ
1
Max
Unit
Notes
Master clock frequency
MCLK
1.544
MHz
must be supplied
Master clock tolerance
MCLKt
±32
ppm
Master clock duty cycle
MCLKd
40
60
%
Transmit clock frequency
TCLK
1.544
MHz
Transmit clock tolerance
TCLKt
±100
ppm
Transmit clock duty cycle
TCLKd
10
90
%
TPOS/TNEG to TCLK setup time
t
SUT
50
ns
TCLK to TPOS/TNEG hold time
t
HT
50
ns
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Table 27. Master and Transmit Clock Timing Characteristics for E1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ
1
Max
Unit
Notes
Master clock frequency
MCLK
2.048
MHz
must be supplied
Master clock tolerance
MCLKt
±32
ppm
Master clock duty cycle
MCLKd
40
60
%
Transmit clock frequency
TCLK
2.048
MHz
Transmit clock tolerance
TCLKt
±100
ppm
Transmit clock duty cycle
TCLKd
10
90
%
TPOS/TNEG to TCLK setup time
t
SUT
50
ns
TCLK to TPOS/TNEG hold time
t
HT
50
ns
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Figure 14. Transmit Clock Timing
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