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參數(shù)資料
| 型號： | M1033-11I173.3708LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1033 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 200K |
| 代理商： | M1033-11I173.3708LF |
M1033/34 Preliminary Information 0.1
4 of 14
Revised 07Apr2005
I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0
Integrated
Circuit
Systems, Inc.
M1033/34
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminar y In f o r m atio n
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz.
P Divider Look-Up Table (LUT)
The P_SEL1 and P_SEL0 pins select the post-PLL divider
value P. The output frequency of the SAW can be
divided by 1 or 2 or the output can be TriStated as
specified in Table 5.
FUNCTIONAL DESCRIPTION
The M1033/34 is a PLL (Phase Locked Loop) based
clock generator that generates an output clock synchro-
nized to one of two selectable input reference clocks.
An internal high ‘Q’ SAW delay line provides low jitter
signal performance.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in Tables 3 and 4 on pg. 3. These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
The M1033/34 includes a Loss of Reference (LOR)
indicator for the currently selected reference input which
can be used to provides status information to system
management software. A Narrow Bandwidth (NBW)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
An automatic input reselection feature, or “AutoSwitch”
is also included in the M1033/34. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails (when LOR goes high).
Reference selection is non-revertive, meaning that only
one reference reselection will be made each time that
AutoSwitch is re-enabled.
In addition to the AutoSwitch feature, a Phase Build-out
option can be ordered with the device.
P_SEL1:0
P Value
M1033-155.5200 or M1034-155.5200
Output Frequency (MHz)
0
2
77.76
0
1
155.52
1
0
2
77.76
1
TriState
N/A
Table 5: P Divider Look-Up Table (LUT)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1033-16-155.5200 | 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M1033-16-155.5200T | 制造商:Integrated Device Technology Inc 功能描述:VCSO 36-Pin CLCC T/R 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR |
| M1034 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| M1034-11-155.5200 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| M1034-11-156.2500 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED CLOCK PLL WITH AUTOSWITCH |
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