- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377801 > M13S128168A-5TG (ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC) 2M x 16 Bit x 4 Banks Double Data Rate SDRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | M13S128168A-5TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| 中文描述： | 8M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66 |
| 文件頁數(shù)： | 20/49頁 |
| 文件大?。?/td> | 1513K |
| 代理商： | M13S128168A-5TG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
ES MT
M13S128168A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8 20/49
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst
and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum
delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
0
1
2
3
4
5
6
7
8
COMMAND
DQS
DQ's
NOP
NO P
NOP
NO P
NOP
NOP
Din A
0
WRITE A
Din A
1
Din B
0
Din B
1
Din B
2
Din B
3
1t
C K
NOP
WRITE B
CLK
CL K
t
C C D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M13S128168A-6BG | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128168A-6T | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128168A-6TG | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128168A-7.5AB | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A | 1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M13S128168A-5TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128168A-6BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128168A-6BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128168A-6T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128168A-6TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。