參數(shù)資料
型號: M13S128168A-7.5AB
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 200萬× 16位× 4個銀行雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 16/49頁
文件大?。?/td> 1513K
代理商: M13S128168A-7.5AB
ES MT
M13S128168A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8 16/49
Essential Functionality for DDR SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and
WE
high at the rising edge of the clock (CLK) after t
RCD
from
the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM
until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
CO MMAND
READ A
NOP
NO P
NOP
NO P
NOP
NOP
NOP
NO P
CL K
CL K
CAS L at enc y =3
DQS
DQ' s
D o u t0 Do u t 1 Do u t2 D o u t3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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