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鍨嬭櫉(h脿o)锛� M1AFS1500-1FGG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 156/334闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 8MB FLASH 1.5M 484-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� Fusion®
RAM 浣嶇附瑷�(j矛)锛� 276480
杓稿叆/杓稿嚭鏁�(sh霉)锛� 223
闁€鏁�(sh霉)锛� 1500000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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Fusion Family of Mixed Signal FPGAs
Revision 4
2-223
Timing Characteristics
Figure 2-143 Input DDR Timing Diagram
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRICLR2Q1
12
3
4
5
6
7
8
9
CLK
Data
CLR
Out_QR
Out_QF
tDDRICLKQ1
2
4
6
3
5
7
tDDRIHD
tDDRISUD
tDDRICLKQ2
Table 2-180 Input DDR Propagation Delays
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
0.39
0.44
0.52
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
0.27
0.31
0.37
ns
tDDRISUD
Data Setup for Input DDR
0.28
0.32
0.38
ns
tDDRIHD
Data Hold for Input DDR
0.00
ns
tDDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR
0.57
0.65
0.76
ns
tDDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR
0.46
0.53
0.62
ns
tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR
0.00
ns
tDDRIRECCLR
Asynchronous Clear Recovery Time for Input DDR
0.22
0.25
0.30
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.22
0.25
0.30
ns
tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR
0.36
0.41
0.48
ns
tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR
0.32
0.37
0.43
ns
FDDRIMAX
Maximum Frequency for Input DDR
1404
1232
1048
MHz
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
24LC16B-I/ST IC EEPROM 16KBIT 400KHZ 8TSSOP
M1A3PE1500-1PQ208I IC FPGA 1KB FLASH 1.5M 208-PQFP
93AA86C-I/P IC EEPROM 16KBIT 3MHZ 8DIP
A3PE1500-1PQG208I IC FPGA 1KB FLASH 1.5M 208-PQFP
24LC08B/ST IC EEPROM 8KBIT 400KHZ 8TSSOP
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