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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� M1AFS1500-1FGG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 329/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 8MB FLASH 1.5M 484-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� Fusion®
RAM 浣嶇附瑷�(j矛)锛� 276480
杓稿叆/杓稿嚭鏁�(sh霉)锛� 223
闁€鏁�(sh霉)锛� 1500000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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Device Architecture
2-78
Revision 4
Timing Characteristics
Table 2-35 FIFO
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
tENS
REN, WEN Setup time
1.34
1.52
1.79
ns
tENH
REN, WEN Hold time
0.00
ns
tBKS
BLK Setup time
0.19
0.22
0.26
ns
tBKH
BLK Hold time
0.00
ns
tDS
Input data (WD) Setup time
0.18
0.21
0.25
ns
tDH
Input data (WD) Hold time
0.00
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.17
2.47
2.90
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
0.94
1.07
1.26
ns
tRCKEF
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
tWCKFF
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
tRSTAF
RESET Low to Almost-Empty/Full Flag Valid
6.13
6.98
8.20
ns
tRSTBQ
RESET Low to Data out Low on RD (flow-through)
0.92
1.05
1.23
ns
RESET Low to Data out Low on RD (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency for FIFO
310
272
231
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
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