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參數(shù)資料
| 型號(hào)： | M2006-01-669.3266 |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC36 |
| 封裝： | 9 X 9 MM, SMT-36 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大小： | 911K |
| 代理商： | M2006-01-669.3266 |
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
4
M2006-01
Prelimnary Specifications
Micro Networks
An Integrated Circuit Systems Company
PIN DESCRIPTIONS
TABLE 2
Pin Number
1, 2, 3
4, 9
5, 8
6, 7
10, 14, 26
11, 19, 33
12, 13
15, 16
17
Name
I/O
Configuration
Description
GND
OP_IN, nOP_IN
nOP_OUT, OP_OUT
nVC, VC
GND
Vcc
FOUT1, nFOUT1
FOUT0, nFOUT0
P1
GND
Analog I/O
Analog I/O
Input
GND
Power
Output
Output
Input
Power Supply Ground
Used for external loop filter. See Figure 2.
Used for external loop filter. See Figure 2.
VCSODifferential Control Voltage Input Pair
Power Supply Ground
Positive Supply Pins
Differential output, 3.3V LVPECL levels.
Differential output, 3.3V LVPECL levels.
Determines the output divider value. LVCMOS / LVTTL
interface levels.
Clocks in serial data present at S_DATA input into the
shift register on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Shift register serial input. Data is sampled on the rising
edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the
dividers. LVCMOS / LVTTL interface levels.
Selects between the different reference clock inputs as
the PLL reference source. LVCMOS / LVTTL interface
levels.
Inverting differential clock input.
LVCMOS / LVTTL interface levels.
Non-inverting differential clock input. LVCMOS / LVTTL
interface levels.
Reference clock input. LVCMOS / LVTTL interface
levels.
Inverting differential clock input. LVPECL levels.
Non-inverting differential clock input.
Increases the output frequency by one output clock
cycle for a given input clock cycle. The added clock
occurs during the next input clock period following the
rising edge of ADD_CLK. Only one output clock can be
added for each input reference clock cycle. LVCMOS /
LVTTL interface levels.
Decreases the output frequency by one output clock
cycle for a given input clock cycle. The deletion occurs
during the next input clock period following the rising
edge of DROP_CLK. Only one output clock can be
deleted for each input reference clock cycle. LVCMOS /
LVTTL interface levels.
Asserting PSL (phase slope limiter) causes a decrease
in the loop bandwidth by reducing the phase detector
gain. LVCMOS / LVTTL interface levels.
No connection. Internal test pins must be left floating.
Unterminated
Unterminated
Pull - down
18
S_CLOCK
Input
Pull - down
20
S_DATA
Input
Pull - down
21
S_LOAD
Input
Pull - down
22, 29
REF_SEL1, REF_SEL0
Input
Pull - down
23
NDIF_CLK0
Input
Pull - up
24
DIF_CLK0
Input
Pull - down
25
REF_CLK
Input
Pull - down
27
28
30
NDIF_CLK1
DIF_CLK1
ADD_CLK
Input
Input
Input
Pull - up
Pull - down
Pull - down
31
DROP_CLK
Input
Pull - down
32
PSL
Input
Pull - down
34, 35, 36
DNC
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