參數(shù)資料
型號(hào)： M24C16-W1MN3T
廠商： 意法半導(dǎo)體
元件分類： DRAM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù)： 11/25頁(yè)
文件大小： 449K
代理商： M24C16-W1MN3T
11/25
M24C16, M24C08, M24C04, M24C02, M24C01
Sequential Read
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master
does
acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must
not
acknowledge the last byte, and
must
generate a Stop condition, as shown in
Figure 10.
.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9
th
bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory
array set to 1 (each byte contains FFh).
相關(guān)PDF資料
PDF描述
M24C16-W1MN6T The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16WMN1T RECTIFIER SBR DUAL 40A 40V 280A-ifsm 530mV-vf 0.5mA-ir ITO-220AB 50/TUBE
M24C16WEA1T The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C16WEA3T The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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