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參數(shù)資料
| 型號： | M24C64-MB3P |
| 廠商： | 意法半導體 |
| 英文描述： | 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 64Kbit和32Kbit串行IC總線的EEPROM |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 394K |
| 代理商： | M24C64-MB3P |
M24C64, M24C32
12/26
Figure 10. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 4
th
bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in
Fig-
ure 10.
) but withoutsending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
Read/Write bit (RW) set to 1. The device acknowl-
edges this, and outputs the contents of the ad-
dressed byte. The bus master must not
acknowledge the byte, and terminates the transfer
with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the Read/Write bit (RW) set
to 1. The device acknowledges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates the transfer with a Stop condi-
tion, as shown in
Figure 10.
, withoutacknowledg-
ing the byte.
S
DEV SEL *
BYTE ADDR
BYTE ADDR
S
DEV SEL
DATA OUT 1
AI01105C
DATA OUT N
S
S
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
S
S
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
S
DATA OUT N
S
DEV SEL *
BYTE ADDR
BYTE ADDR
SEQUENTIAL
RANDOM
READ
S
DEV SEL *
DATA OUT 1
S
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M24C64-MB3T | 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85 |
| M24C64-WMN3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64-WMN3TP | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64-WMN6 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64-WMN6P | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M24C64M-FCU6T/TF | 功能描述:64KBIT SERIAL I2C BUS EEPROM 制造商:stmicroelectronics 系列:- 包裝:剪切帶（CT） 零件狀態(tài):停產(chǎn) 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:64K（8K x 8） 速度:100kHz，400kHz，1MHz 接口:I2C，2 線串口 電壓 - 電源:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:4-XFBGA 供應商器件封裝:4-WLCSP 標準包裝:1 |
| M24C64-MN6 | 功能描述:電可擦除可編程只讀存儲器 5.5V 64K (8Kx8) RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M24C64MN6T | 制造商:ST MICRO 功能描述:* 制造商:STMicroelectronics 功能描述: |
| M24C64-MN6T | 制造商:STMicroelectronics 功能描述: |
| M24C64-MW6 | 功能描述:電可擦除可編程只讀存儲器 5.5V 64K (8Kx8) RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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