參數(shù)資料
型號(hào): M24C64-MB3P
廠商: 意法半導(dǎo)體
英文描述: 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
中文描述: 64Kbit和32Kbit串行IC總線的EEPROM
文件頁(yè)數(shù): 6/26頁(yè)
文件大?。?/td> 394K
代理商: M24C64-MB3P
M24C64, M24C32
6/26
Figure 5. I
2
C Bus Protocol
Table 3. Device Select Code
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 4. Most Significant Byte
Table 5. Least Significant Byte
Device Type Identifier
1
Chip Enable Address
2
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device Select Code
1
0
1
0
E2
E1
E0
RW
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1
2
3
7
8
9
MSB
ACK
START
Condition
SCL
1
2
3
7
8
9
MSB
ACK
STOP
Condition
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
相關(guān)PDF資料
PDF描述
M24C64-MB3T 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
M24C64-WMN3T The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C64-WMN3TP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C64-WMN6 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C64-WMN6P The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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