參數(shù)資料
型號: M24C64-MN3
廠商: 意法半導體
英文描述: 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
中文描述: 64Kbit和32Kbit串行IC總線的EEPROM
文件頁數(shù): 13/26頁
文件大?。?/td> 394K
代理商: M24C64-MN3
13/26
M24C64, M24C32
Sequential Read
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master doesacknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must notacknowledge the last byte, and must
generate a Stop condition, as shown in
Figure 10.
.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9
th
bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory
array set to 1 (each byte contains FFh).
相關PDF資料
PDF描述
M24C64-MN3P 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
M24C64-MN3T 16-Bit Transparent D-Type Latch With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85
M24C64-MN3TP 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TSSOP -40 to 85
M24C64-MN6 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
M24C64-MN6P 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TVSOP -40 to 85
相關代理商/技術參數(shù)
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