參數(shù)資料
型號(hào)： M25P20VMN6T
廠商： 意法半導(dǎo)體
元件分類(lèi)： DRAM
英文描述： 4 Mbit Uniform Sector, Serial Flash Memory
中文描述： 4兆位統(tǒng)一部門(mén)，串行閃存
文件頁(yè)數(shù)： 12/34頁(yè)
文件大?。?/td> 217K
代理商： M25P20VMN6T
M25P05-A
12/34
Figure 11. Write Status Register (WRSR) Instruction Sequence
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (WRSR) instruction
is not executed. As soon as Chip Select (S) is driv-
en High, the self-timed Write Status Register cycle
(whose duration is t
W
) is initiated. While the Write
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complet-
ed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 2. The Write Status Register (WRSR) in-
struction also allows the user to set or reset the
Status Register Write Disable (SRWD) bit in ac-
cordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not execut-
ed once the Hardware Protected Mode (HPM) is
entered.
C
D
AI02282D
S
Q
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15
High Impedance
Instruction
Status
Register In
0
7
6
5
4
3
2
0
1
MSB
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M25P20-VMN6T 功能描述:閃存 3.0V 2M (256Kx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線(xiàn)寬度:1 bit 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類(lèi)型: 接口類(lèi)型:SPI 訪(fǎng)問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M25P20VMN6TG 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface
M25P20-VMN6TG/X 制造商:NUMONYX 制造商全稱(chēng):Numonyx B.V 功能描述:2 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface
M25P20VMN6TP 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface
M25P20-VMN6TP 功能描述:閃存 Lo-Volt 2M (256Kx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線(xiàn)寬度:1 bit 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類(lèi)型: 接口類(lèi)型:SPI 訪(fǎng)問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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