參數(shù)資料
型號: M25P40-VMN3G
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 24/40頁
文件大?。?/td> 232K
代理商: M25P40-VMN3G
M25P40
24/40
Release from Deep Power-down and Read
Electronic Signature (RES)
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. Executing this
instruction takes the device out of the Deep Pow-
er-down mode.
The instruction can also be used to read, on Serial
Data Output (Q), the 8-bit Electronic Signature,
whose value for the
M25P40
is
12h
.
Except while an Erase, Program or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Electronic Signature
(RES) instruction always provides access to the 8-
bit Electronic Signature of the device, and can be
applied even if the Deep Power-down mode has
not been entered.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in
progress, is not decoded, and has no effect on the
cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code is followed by 3
dummy bytes, each bit being latched-in on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Then, the 8-bit Electronic Signature,
stored in the memory, is shifted out on Serial Data
Output (Q), each bit being shifted out during the
falling edge of Serial Clock (C).
The instruction sequence is shown in
Figure 18.
.
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction is terminat-
ed by driving Chip Select (S) High after the Elec-
tronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S) is driven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is
put in the Stand-by Power mode. If the device was
not previously in the Deep Power-down mode, the
transition to the Stand-by Power mode is immedi-
ate. If the device was previously in the Deep Pow-
er-down mode, though, the transition to the Stand-
by Power mode is delayed by t
RES2
, and Chip Se-
lect (S) must remain High for at least t
RES2
(max),
as specified in
Table 17.
. Once in the Stand-by
Power mode, the device waits to be selected, so
that it can receive, decode and execute instruc-
tions.
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Sequence and Data-Out Sequence
Note: The value of the 8-bit Electronic Signature, for the M25P40, is 12h.
C
D
AI04047C
S
Q
23
2
1
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35
22 21
3
2
1
0
36 37 38
7
6
5
4
3
2
0
1
High Impedance
Electronic Signature Out
Instruction
3 Dummy Bytes
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
t
RES2
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