參數(shù)資料
型號: M25P64-VMF6P
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 31/38頁
文件大小: 519K
代理商: M25P64-VMF6P
31/38
M25P64
Table 14. AC Characteristics
Note: 1. t
CH
+ t
CL
must be greater than or equal to 1/ f
C
(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Test conditions specified in
Table 10.
and
Table 11.
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
f
C
f
C
Clock Frequency for the following instructions: FAST_READ,
PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR
D.C.
50
MHz
f
R
Clock Frequency for READ instructions
D.C.
20
MHz
t
CH (1)
t
CLH
Clock High Time
9
ns
t
CL (1)
t
CLL
Clock Low Time
9
ns
t
CLCH (2)
Clock Rise Time
3
(peak to peak)
0.1
V/ns
t
CHCL (2)
Clock Fall Time
3
(peak to peak)
0.1
V/ns
t
SLCH
t
CSS
S Active Setup Time (relative to C)
5
ns
t
CHSL
S Not Active Hold Time (relative to C)
5
ns
t
DVCH
t
DSU
Data In Setup Time
2
ns
t
CHDX
t
DH
Data In Hold Time
5
ns
t
CHSH
S Active Hold Time (relative to C)
5
ns
t
SHCH
S Not Active Setup Time (relative to C)
5
ns
t
SHSL
t
CSH
S Deselect Time
100
ns
t
SHQZ (2)
t
DIS
Output Disable Time
8
ns
t
CLQV
t
V
Clock Low to Output Valid
8
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
HLCH
HOLD Setup Time (relative to C)
5
ns
t
CHHH
HOLD Hold Time (relative to C)
5
ns
t
HHCH
HOLD Setup Time (relative to C)
5
ns
t
CHHL
HOLD Hold Time (relative to C)
5
ns
t
HHQX (2)
t
LZ
HOLD to Output Low-Z
8
ns
t
HLQZ (2)
t
HZ
HOLD to Output High-Z
8
ns
t
WHSL (4)
Write Protect Setup Time
20
ns
t
SHWL (4)
Write Protect Hold Time
100
ns
t
W
Write Status Register Cycle Time
5
15
ms
t
PP
Page Program Cycle Time
1.4
5
ms
t
SE
Sector Erase Cycle Time
1
3
s
t
BE
Bulk Erase Cycle Time
68
160
s
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