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參數(shù)資料
| 型號(hào)： | M25P80VMN6T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁(yè)數(shù)： | 19/34頁(yè) |
| 文件大?。?/td> | 217K |
| 代理商： | M25P80VMN6T |
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M25P05-A
Figure 17. Deep Power-down (DP) Instruction Sequence
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this
mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
to reduce the standby current (from I
CC1
to I
CC2
,
as specified in Table 12).
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. This releases
the device from this mode. The Release from
Deep Power-down and Read Electronic Signature
(RES) instruction also allows the Electronic Signa-
ture of the device to be output on Serial Data Out-
put (Q).
The Deep Power-down mode automatically stops
at Power-down, and the device always Powers-up
in the Standby mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruc-
tion is not executed. As soon as Chip Select (S) is
driven High, it requires a delay of t
DP
before the
supply current is reduced to I
CC2
and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
C
D
AI03753D
S
2
1
3
4
5
6
7
0
t
DP
Deep Power-down Mode
Stand-by Mode
Instruction
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M25P32 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P40 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE10-VMN6G | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE20-VMP6TP | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE10-VMN6P | 4 Mbit Uniform Sector, Serial Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25P80-VMN6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit, Low Voltage, Serial Flash Memory With 25 MHz SPI Bus Interface |
| M25P80VMN6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
| M25P80-VMN6TG | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface |
| M25P80VMN6TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
| M25P80-VMN6TP | 功能描述:IC FLASH 8MBIT 75MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:Forté™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:256K (32K x 8) 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:28-TSSOP（0.465"，11.8mm 寬） 供應(yīng)商設(shè)備封裝:28-TSOP 包裝:帶卷 (TR) 其它名稱:71V256SA15PZGI8 |
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