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參數(shù)資料
| 型號： | M29F016D90N1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Mbit (2Mb x8, Uniform Block) 5V Supply Flash Memory |
| 中文描述： | 16兆位（含2Mb × 8，統(tǒng)一座）5V電源快閃記憶體 |
| 文件頁數(shù)： | 8/37頁 |
| 文件大小： | 536K |
| 代理商： | M29F016D90N1T |
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M29F016D
8/37
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma-
chine.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table 13 and Figure 13, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
OL
. Ready/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 13 and Figure
13, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
V
CC
Supply Voltage (5V).
V
CC
power supply for all operations (Read, Program
and Erase).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1μF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply, see Figure 10, AC Measurement Load Cir-
cuit.
The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC3
.
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
provides
the
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