參數(shù)資料
型號(hào): M29F040-150XN1TR
廠商: 意法半導(dǎo)體
英文描述: Low-Noise High-Speed JFET-Input Operational Amplifier 8-PDIP
中文描述: 4兆位512KB的× 8,統(tǒng)一座單電源閃存
文件頁數(shù): 5/31頁
文件大小: 232K
代理商: M29F040-150XN1TR
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.
7th Cyc.
RST
(4,10)
Read Array/
Reset
1+
Addr.
(3,7)
X
Read Memory Array until a new write cycle is initiated.
Data
F0h
3+
Addr.
(3,7)
5555h
2AAAh
5555h
Read Memory Array until a new write
cycle is initiated.
Data
AAh
55h
F0h
RSIG
(4)
Read
Electronic
Signature
3+
Addr.
(3,7)
5555h
2AAAh
5555h
Read Electronic Signature until a new
write cycle is initiated. See Note 5.
Data
AAh
55h
90h
RBP
(4)
Read Block
Protection
3+
Addr.
(3,7)
5555h
2AAAh
5555h
Read Block Protection until a new write
cycle is initiated. See Note 6.
Data
AAh
55h
90h
PG
Program
4
Addr.
(3,7)
5555h
2AAAh
5555h
Program
AddressRead Data Polling or Toggle Bit
until Program completes.
Program
Data
Data
AAh
55h
A0h
BE
Block Erase
6
Addr.
(3,7)
5555h
2AAAh
5555h
5555h
2AAAh
Block
Address
Additional
Block
(8)
Data
AAh
55h
80h
AAh
55h
30h
30h
CE
Chip Erase
6
Addr.
(3,7)
5555h
2AAAh
5555h
5555h
2AAAh
5555h
Note 9
Data
AAh
55h
80h
AAh
55h
10h
ES
Erase
Suspend
1
Addr.
(3,7)
X
Read until Toggle stops, then read all the data needed from any
uniform block(s) not being erased then Resume Erase.
Data
B0h
ER
Erase
Resume
1
Addr.
(3,7)
X
Read Data Polling or Toggle Bit until Erase completes or Erase
is suspended another time
Data
30h
Notes:
1. Command not interpreted in this table will default to read array mode.
2. While writing any command or during RSG and RSP execution, the P/E.C. can be reset by writing the command 00h to the C.I.
3. X = Don’t Care.
4. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or
Electronic Signature codes. Any number of read cycles can occur after one command cycle.
5. Signature Address bits A0, A1, A6 at V
IL
will output Manufacturer code (20h). Address bits A0 at V
IH
and A1, A6 at V
IL
will output
Device code.
6. Protection Address: A0, A6 at V
IL
, A1 at V
IH
and A16, A17, A18 within the uniform block to be checked, will output the Block Protection
status.
7. Address bits A15-A18 are don’t care for coded address inputs.
8. Optional, additional blocks addresses must be entered within a 80
μ
s delay after last write entry, timeout status can be verified
through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
9. Read Data Polling or Toggle bit until Erase completes.
10. A wait time of 5
μ
s is necessary after a Reset command, if the memory is in a Block Erase status, before starting
any operation.
Table 6. Instructions
(1,2)
5/31
M29F040
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