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參數(shù)資料
| 型號： | M29W008T-100N1TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TV 22C 22#22D PIN WALL RECP |
| 中文描述： | 8兆1兆× 8，啟動塊低壓單電源閃存 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 219K |
| 代理商： | M29W008T-100N1TR |
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Symbol
Alt
Parameter
M29W008T / M29W008B
Unit
-120
-150
V
CC
= 2.7V to 3.6V
V
CC
= 2.7V to 3.6V
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
120
150
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
50
65
ns
t
DVWH
t
DS
Input Valid to Write Enable High
50
65
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
0
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
30
35
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
0
0
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
50
65
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μ
s
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
t
PHPHH
(1,2)
t
VIDR
RP Rise Time to V
ID
500
500
ns
t
PLPX
t
RP
RP Pulse Width
500
500
ns
t
WHRL
(1)
t
BUSY
Program Erase Valid to RB Delay
90
90
ns
t
PHWL (1)
t
RSP
RP High to Write Enable Low
4
4
μ
s
Notes:
1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Table 15B. Write AC Characteristics, Write Enable Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C)
During the execution of the erase by the P/E.C., the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in order to
reset the P/E.C.
Chip Erase (CE) Instruction.
This instruction uses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on the third cycle after
the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts and
the device is reset to Read Array. It is not necessary
to program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh. Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the execu-
tion of the erase by the P/E.C., Data Polling bit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
stop when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has been
an Erase Failure.
19/30
M29W008T, M29W008B
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| M29W008T-100N6TR | TV 22C 22#22D PIN RECP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M29W008T-100N5TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash Memory |
| M29W008T-100N6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash Memory |
| M29W008T-120N1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash Memory |
| M29W008T-120N5TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash Memory |
| M29W008T-120N6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash Memory |
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