參數資料
型號： M29W640DT90N6F
廠商： 意法半導體
英文描述： 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory
中文描述： 64兆位和8Mb x8或4Mb的x16插槽，啟動塊3V電源快閃記憶體
文件頁數： 10/49頁
文件大?。?/td> 945K
代理商： M29W640DT90N6F
M29W640DT, M29W640DB
10/49
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 2.
and
Table 3., Bus Operations, BYTE =
V
IH
, for a summary. Typically glitches of less than
5ns on Chip Enable or Write Enable are ignored by
the memory and do not affect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see
Figure 9., Read Mode AC Waveforms
,
and
Table 12., Read AC Characteristics
, for de-
tails of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See
Figure 10.
and
Figure
11., Write AC Waveforms, Chip Enable Con-
trolled
, and
Table 13.
and
Table 14., Write AC
Characteristics, Chip Enable Controlled
, for de-
tails of the timing requirements.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
be held within V
CC
± 0.2V. For the Standby current
level see
Table 11., DC Characteristics
.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
, for Program or Erase operations un-
til the operation completes.
Automatic Standby.
If CMOS levels (V
CC
± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
ID
to be applied to some pins.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in
Table 2.
and
Table 3., Bus Operations,
BYTE = V
IH
.
Block Protect and
Chip Unprotect.
Groups
blocks can be protected against accidental Pro-
gram or Erase. The Protection Groups are shown
in
APPENDIX A.
,
Table 19.
and
Table 20., Bottom
Boot Block Addresses, M29W640DB
. The whole
chip can be unprotected to allow the data inside
the blocks to be changed.
The V
PP
/Write Protect
pin can be used to protect
the two outermost boot blocks. When V
PP
/Write
Protect
is at V
IL
the two outermost boot blocks are
protected and remain protected regardless of the
Block Protection Status or the Reset/Block Tem-
porary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in
APPENDIX D.
.
of
Table 2. Bus Operations, BYTE = V
IL
Operation
E
G
W
Address Inputs
DQ15A–1, A0-A21
Data Inputs/Outputs
DQ14-DQ8
DQ7-DQ0
Bus Read
V
IL
V
IL
V
IH
Cell Address
Hi-Z
Data Output
Bus Write
V
IL
V
IH
V
IL
Command Address
Hi-Z
Data Input
Output Disable
X
V
IH
V
IH
X
Hi-Z
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
IH
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
Hi-Z
20h
相關PDF資料
PDF描述
M29W640DB90N6F 64 megabit and 8Mb X8 or 4Mb x16 slot, the boot block 3V supply flash memory
M29W640DT70ZA6E 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory
M29W640DB70ZA6E 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory
M29W640DT90ZA6E 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory
M29W640DB90ZA6E 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory
相關代理商/技術參數
參數描述
M29W640DT90ZA6 功能描述:閃存 8Mx8 or 4Mx16 90ns RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M29W640FB70N6E 功能描述:閃存 64 Mbit Boot Block 3V STD 閃存 RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M29W640FB70N6F 功能描述:閃存 64MB RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M29W640FB70ZA6E 功能描述:閃存 STD FLASH RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M29W640FB70ZA6F 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 70ns 48-Pin TFBGA T/R 制造商:Micron Technology Inc 功能描述:64MBIT PARALLEL NOR FLASH 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 64MBIT 8MX8/4MX16 70NS 48TFBGA - Tape and Reel
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