參數(shù)資料
型號(hào): M29W800AB80ZA5T
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
中文描述: 8兆1兆x8或512KB的x16插槽,引導(dǎo)塊低壓?jiǎn)坞娫撮W存
文件頁(yè)數(shù): 20/33頁(yè)
文件大?。?/td> 234K
代理商: M29W800AB80ZA5T
M29W800AT, M29W800AB
20/33
Table 19. Write AC Characteristics, E Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C)
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol
Alt
Parameter
M29W800AT / M29W800AB
Unit
80
90
V
CC
= 3.0V to 3.6V
CL = 30pF
V
CC
= 3.0V to 3.6V
CL = 30pF
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
80
90
ns
t
AVEL
t
AS
Address Valid to Chip Enable Low
0
0
ns
t
DVEH
t
DS
Input Valid to Chip Enable High
35
45
ns
t
EHDX
t
DH
Chip Enable High to Input Transition
0
0
ns
t
EHEL
t
CPH
Chip Enable High to Chip Enable Low
30
30
ns
t
EHGL
t
OEH
Chip Enable High to Output Enable Low
0
0
ns
t
EHRL(1)
t
BUSY
Program Erase Valid to RB Delay
80
90
ns
t
EHWH
t
WH
Chip Enable High to Write Enable High
0
0
ns
t
ELAX
t
AH
Chip Enable Low to Address Transition
45
45
ns
t
ELEH
t
CP
Chip Enable Low to Chip Enable High
35
35
ns
t
GHEL
Output Enable High Chip Enable Low
0
0
ns
t
PHPHH(1, 2)
t
VIDR
RP Rise TImeto V
ID
500
500
ns
t
PHWL(1)
t
RSP
RP High to Write Enable Low
4
4
μ
s
t
PLPX
t
RP
RP Pulse Width
500
500
ns
t
VCHWL
t
VCS
V
CC
High to Write Enable Low
50
50
μ
s
t
WLEL
t
WS
Write Enable Low to Chip Enable Low
0
0
ns
POWER SUPPLY
Power Up
The memory Command Interface is reset on pow-
er up to Read Array. The device does not accept
commands on the first rising edge of W, if both W
and E are at V
IL
with G at V
IH
during power-up.
Any write cycle initiation is blocked when V
CC
is
below V
LKO
.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the V
CC
rail decoupled with a 0.1
μ
F capacitor
close to the V
CC
and V
SS
pins. The PCB trace
widths should be sufficient to carry the V
CC
pro-
gram and erase currents required.
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