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參數(shù)資料
| 型號： | M29W800AT80ZA5T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory |
| 中文描述： | 8兆1兆x8或512KB的x16插槽，引導(dǎo)塊低壓單電源閃存 |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 234K |
| 代理商： | M29W800AT80ZA5T |
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M29W800AT, M29W800AB
Table 8. Commands
Hex Code
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read ElectronicSignature, Read BlockPro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structions require from 1 to6 cycles, thefirst orfirst
three of which are alwayswrite operations used to
initiate the instruction. They are followed by either
further writecycles to confirm the first command or
execute thecommand immediately. Commandse-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum datasecurity. In-
structions are initialised by two initial Codedcycles
which unlock the Command Interface. In addition,
for Erase, instructionconfirmation isagain preced-
ed by the two Coded cycles.
Status Register Bits
P/E.C. statusisindicated during executionby Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand execution will automatically output these
five Status Register bits. The P/E.C. automatically
sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other
bits (DQ0, DQ1 and DQ4) are reserved for future
use and should bemasked. See Tables 10 and 11.
Data Polling Bit (DQ7).
When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be per-
formed at the address being programmed or at an
address within the block being erased. If all the
blocks selectedfor erasure are protected,DQ7 will
be set to ’0’for about 100
μ
s, and then returnto the
previous addressed memory data value. See Fig-
ure 13 for the Data Polling flowchart and Figure 12
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be provid-
ed. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
on a block being erased and thedata value on oth-
er blocks. During Programoperation in EraseSus-
pend Mode, DQ7 will have the same behavior as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6).
When Programming or Eras-
ing operations are in progress, successive at-
tempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G,
or E when G is low. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last pro-
grammed ora ’1’after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. If the blocks selected for
erasure are protected, DQ6 will toggle for about
100
μ
s and then return back to Read. DQ6 will be
set to ’1’ if a Read operation is attempted on an
Erase Suspend block. When erase is suspended
DQ6 will toggle during programming operations in
a block different to the blockin Erase Suspend. Ei-
ther E or G toggling will cause DQ6 to toggle. See
Figure 14 for Toggle Bit flowchart and Figure 15
for Toggle Bit waveforms.
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PDF描述 |
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| M29W800AB90M6T | Circular Connector; No. of Contacts:12; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-97 |
| M29W800AB90M5T | Circular Connector; No. of Contacts:37; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-37 |
| M29W800AB90M1T | Circular Connector; No. of Contacts:37; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-37 |
| M29W800AB90N1T | Circular Connector; No. of Contacts:55; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:16-55 |
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| M29W800AT90M1 | 功能描述:閃存 1Mx8 or 512Kx16 90ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W800AT90N1 | 功能描述:閃存 1Mx8 or 512Kx16 90ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W800AT90N6 | 功能描述:閃存 1Mx8 or 512Kx16 90ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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