參數(shù)資料
型號(hào): M2V56S20ATP-7
廠商: Mitsubishi Electric Corporation
英文描述: 256M Synchronous DRAM
中文描述: 256M同步DRAM
文件頁(yè)數(shù): 21/49頁(yè)
文件大?。?/td> 244K
代理商: M2V56S20ATP-7
Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
21
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed.
WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"Don't Care".
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Write
Yb
0
00
Dc0
Dc1
Dc2
Dc3
Write
Ya
0
00
Da0
Da1
Da2
Db0
Write
Yc
0
10
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
Xa
Xa
00
Write interrupted by Read (CL=2, BL=4)
READ
Yb
0
00
Da0
Da1
Qb0
Write
Ya
0
00
Qb1
Qb2
Qb3
don't care
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