參數(shù)資料
型號: M2V56S20ATP-7
廠商: Mitsubishi Electric Corporation
英文描述: 256M Synchronous DRAM
中文描述: 256M同步DRAM
文件頁數(shù): 31/49頁
文件大?。?/td> 244K
代理商: M2V56S20ATP-7
Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
31
AC TIMING REQUIREMENTS
(Ta=0 ~ 70
°
C, Vdd = VddQ = 3.3
±
0.3V, Vss = VssQ = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level:
1.4V
120000
7.8
15
15
15
20
45
20
75
67.5
0.8
1.5
10
1
2.5
2.5
7.5
10
-6
ns
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.8
7.8
20
20
20
20
20
20
20
20
20
20
120000
50
120000
50
80
80
70
70
1
2
1
2
10
1
10
1
3
3
3
3
10
13
10
10
Average Refresh Interval
Mode Register Set Cycle time
ACT to ACT Delay time
Write Recovery time
Row Precharge time
Row Active time
Row to Column Delay
Refresh Cycle time
Row Cycle time
Input Hold time (all inputs)
Input Setup time (all inputs)
Transition time of CLK
CLK Low pulse width
CLK High pulse width
tREF
tRSC
tRRD
tWR
tRP
tRAS
tRCD
tRFC
tRC
tIH
tIS
tT
tCL
tCH
CL=3
CL=2
CLK cycle time
tCLK
Note
Unit
Max.
Min.
Max.
Min.
Max.
Min.
-8
-7
Limits
Parameter
Symbol
AC timing is referenced to the
input signal crossing through 1.4V.
CLK
Signal
1.4V
1.4V
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