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參數(shù)資料
| 型號： | M2V56S30ATP-6 |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, TSOP2-54 |
| 文件頁數(shù)： | 4/51頁 |
| 文件大?。?/td> | 430K |
| 代理商： | M2V56S30ATP-6 |
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12
MITSUBISHI ELECTRIC
May '02
MITSUBISHI LSIs
SDRAM (Rev.1.41)
Single Data Rate
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
Address
Command
Action
RE-
FRESHING
H
X
DESEL
NOP (Idle after tRFC)
L
H
X
NOP
NOP (Idle after tRFC)
L
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
L
H
BA, RA
ACT
ILLEGAL
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
H
X
REFA
ILLEGAL
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MODE
REGISTER
SETTING
H
X
DESEL
NOP (Idle after tRSC)
L
H
X
NOP
NOP (Idle after tRSC)
L
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
L
H
BA, RA
ACT
ILLEGAL
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
H
X
REFA
ILLEGAL
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending
on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Refer to Read with Auto-Precharge in page 26
7. Refer to Write with Auto-Precharge in page 25
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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| M2V56S30ATP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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| M2V56S30TP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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| M2V56S30TP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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