Clock synchronous serial I/O mode
82
Unde
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.75. Typical transmit/receive timings in clock synchronous serial I/O mode
Example of transmit timing (when internal clock is selected)
Example of receive timing (when external clock is selected)
Tc = T
CLK
= 2(n + 1) / fi
fi: frequency of BRG0 count source (f
1
, f
8
, f
32
, fc)
n: value set to BRG0
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLK0
TxD0
Transmit
register empty
flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings:
Internal clock is selected.
CLK polarity select bit = “0”.
Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
1 / f
EXT
Dummy data is set in UART0 transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLK0
RxD0
Receive complete
flag (Rl)
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UART0 transmit buffer register to UART0 transmit register
Read out from UART0 receive buffer register
The above timing applies to the following settings:
External clock is selected.
CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Transferred from UART0 receive register
to UART0 receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
Transmit enable bit “1”
Receive enable bit “1”
Dummy data write to UART0 transmit buffer register
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc
T
CLK
Stopped pulsing because transfer enable bit = “0”
Data is set in UART0 transmit buffer
register
Transferred from UART0 transmit buffer register to UART0
transmit register
Cleared to “0” when interrupt request is accepted, or cleared by software
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7