參數(shù)資料
型號(hào)： M30290MAV-XXXHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 6/32頁
文件大?。?/td> 218K
代理商： M30290MAV-XXXHP
M16C/29 Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit(CPU)
Rev.0.30 2004.06.15
page 14 of 30
REJ03B0072-0030Z
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”.
The I flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
相關(guān)PDF資料
PDF描述
M30291M6V-XXXHP 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP64
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30290MA-XXXHP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
M30290MCT-XXXHP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
M30290MCV-XXXHP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
M30290MC-XXXHP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
M30290T2-CPE 功能描述:EMULATOR COMPACT M16C/26A/28/29 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標(biāo)準(zhǔn)包裝:1 系列:* 類型:* 適用于相關(guān)產(chǎn)品:* 所含物品:*
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