參數(shù)資料
型號: M30302M8-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, PLASTIC, QFP-100
文件頁數(shù): 67/177頁
文件大?。?/td> 2355K
代理商: M30302M8-XXXGP
Timing (Vcc = 5V)
159
Mitsubishi microcomputers
M16C / 30 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BCLK
CSi
ALE
RD
4ns.min
Hi–Z
DB
40ns.min
0ns.min
ADi
BHE
Read timing
BCLK
CSi
ALE
4ns.min
th(WR–AD)
ADi
BHE
(tcyc–40)ns.min
0ns.min
DBi
Write timing
td(BCLK–RD)
0ns.min
th(RD–AD)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Measuring conditions :
VCC=5V
Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V
Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V
WR,WRL,
WRH
td(BCLK–CS)
25ns.max
tcyc
th(BCLK–CS)
4ns.min
th(RD–CS)
0ns.min
th(BCLK–AD)
td(BCLK–AD)
25ns.max
td(BCLK–ALE) 25ns.max
th(BCLK–ALE)
–4ns.min
th(BCLK–RD)
0ns.min
25ns.max
tac2(RD–DB)
th(RD–DB)
tSU(DB–RD)
td(BCLK–CS)
25ns.max
tcyc
th(BCLK–CS)
4ns.min
th(WR–CS)
0ns.min
th(BCLK–AD)
td(BCLK–AD)
25ns.max
td(BCLK–ALE)
25ns.max
th(BCLK–ALE)
–4ns.min
th(BCLK–WR)
0ns.min
td(BCLK–WR)
25ns.max
th(BCLK–DB)
4ns.min
td(BCLK–DB)
40ns.max
td(DB–WR)
th(WR–DB)
VCC = 5V
Figure 1.23.5. VCC = 5V timing diagram (4)
相關(guān)PDF資料
PDF描述
M30302MC-XXXFP 16-BIT, MROM, MICROCONTROLLER, PQFP100
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