參數(shù)資料
型號(hào): M30302MAL-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 16/168頁
文件大?。?/td> 2424K
代理商: M30302MAL-XXXGP
Clock synchronous serial I/O mode
109
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.16.14.)
The multiple pins function is valid only when the internal clock is selected for UART1.
Figure 1.16.14. The transfer clock output from the multiple pins function usage
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
CLK
IN
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
(e) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure 1.16.15 shows the example of serial data
logic switch timing.
Figure 1.16.15. Serial data logic switch timing
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Transfer clock
TxD2
(no reverse)
TxD2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
When LSB first
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