參數(shù)資料
型號(hào): M30302MAL-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 64/168頁
文件大小: 2424K
代理商: M30302MAL-XXXGP
Electrical characteristics
153
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to
85oC (Note 3), CM15 = “1” unless otherwise specified)
Table 1.26.21. Memory expansion and microprocessor modes (with no wait)
Symbol
Standard
Measuring condition
Max.
Min.
Parameter
Unit
td(BCLK-AD)
Address output delay time
50
ns
th(BCLK-AD)
Address output hold time (BCLK standard)
4
ns
th(BCLK-CS)
Chip select output hold time (BCLK standard)
4
ns
td(BCLK-ALE)
ALE signal output delay time
40
ns
th(BCLK-ALE)
ALE signal output hold time
–4
ns
td(BCLK-RD)
RD signal output delay time
40
ns
th(BCLK-RD)
RD signal output hold time
0
ns
td(BCLK-WR)
WR signal output delay time
40
ns
th(BCLK-WR)
WR signal output hold time
0
ns
td(BCLK-DB)
Data output delay time (BCLK standard)
50
ns
th(BCLK-DB)
Data output hold time (BCLK standard)
4
ns
th(WR-DB)
Data output hold time (WR standard)(Note2)
0
ns
td(DB-WR)
Data output delay time (WR standard)
ns
(Note1)
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
f(BCLK) X 2
10 9
– 50
[ns]
td(BCLK-CS)
Chip select output delay time
50
ns
th(RD-AD)
Address output hold time (RD standard)
0
ns
th(WR-AD)
Address output hold time (WR standard)
0
ns
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1k
, hold time
of output “L” level is
t = – 30pF X 1k
X ln (1 – 0.2VCC / VCC)
= 6.7ns.
DBi
R
C
Note 3: Specify a product of -40°C to 85°C to use it.
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
30pF
Figure 1.26.1. Port P0 to P10 measurement circuit
Figure 1.26.1
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