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| 型號(hào)： | M30600E8GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 115/139頁(yè) |
| 文件大?。?/td> | 1782K |
| 代理商： | M30600E8GP |
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
77
Item
Specification
Transfer data format
Transfer data length: 8 bits
Transfer clock
When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) : fi/ 2(n+1)(Note 1) fi = f1, f8, f32
When external clock is selected (bit 3 at addresses 03A016, 03A816 = “1”) : Input from CLKi pin (Note 2)
Transmission/reception control
_______
CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition
To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______
_
When CTS function selected, CTS input level = “L”
Furthermore, if external clock is selected, the following requirements must also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “0”: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “1”: CLKi input level = “L”
Reception start condition
To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
Furthermore, if external clock is selected, the following requirements must also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “0”: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “1”: CLKi input level = “L”
Interrupt request
When transmitting
generation timing
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
When receiving
_
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Select function
Polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
Transfer clock output from multiple pins selection (Note 4)
UART1 transfer clock can be chosen by software to be output from one of the two pins set
_______ _______
Separate CTS/RTS pins (Note 4)
_______
UART0's CTS and RTS pins each can be assigned to separate pins
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.31 lists the specifications
of the clock synchronous serial I/O mode. Figure 1.62 shows a configuration of the UARTi transmit/receive mode register.
Table 1.31. Specifications of clock synchronous serial I/O mode
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
_______ _______
Note 4: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
Clock synchronous serial I/O mode
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相關(guān)代理商/技術(shù)參數(shù) |
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| M30-6011046 | 制造商:Harwin 功能描述: |
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