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參數(shù)資料
| 型號(hào)： | M306NNMG-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-128 |
| 文件頁數(shù)： | 35/72頁 |
| 文件大?。?/td> | 649K |
| 代理商： | M306NNMG-XXXGP |
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Rev.2.10
Aug 25, 2006
page 38 of 67
REJ03B0061-0210
M16C/6N Group (M16C/6NL, M16C/6NN)
5. Electric Characteristics
Under development
This document is under development and its contents are subject to change.
15
ns
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
Symbol
Parameter
Min.
Standard
Unit
Max.
62.5
25
tC
tw(H)
tw(L)
tr
tf
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.11 External Clock Input (XIN Input)
Table 5.12 Memory Expansion Mode and Microprocessor Mode
(NOTE 1)
(NOTE 2)
(NOTE 3)
ns
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
Data input access time (when accessing multiplexed bus area)
Data input setup time
________
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
RDY input hold time
__________
HOLD input hold time
Symbol
Parameter
Min.
Standard
Unit
Max.
40
30
40
0
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5
109
f(BCLK)
– 45 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5)
109
f(BCLK)
– 45 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
(n –0.5)
109
f(BCLK)
– 45 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
VCC = 5 V
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