參數(shù)資料
型號(hào)： M306NNMG-XXXGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP128
封裝： 14 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-128
文件頁(yè)數(shù)： 64/72頁(yè)
文件大小： 649K
代理商： M306NNMG-XXXGP
Rev.2.10
Aug 25, 2006
page 65 of 67
REJ03B0061-0210
M16C/6N Group (M16C/6NL, M16C/6NN)
5. Electric Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 5.18 Timing Diagram (7)
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
td(BCLK-CS)
40ns.max
ADi
td(BCLK-AD)
40ns.max
ALE
th(BCLK-ALE)
-4ns.min
RD
40ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(RD-CS)
th(RD-AD)
BHE
ADi
/DBi
th(RD-DB)
0ns.min
td(AD-ALE)
Read timing
td(BCLK-WR)
40ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
40ns.max
ADi
td(BCLK-AD)
40ns.max
ALE
40ns.max
th(BCLK-ALE)
-4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
50ns.max
4ns.min
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
ADi
/DBi
Data output
WR,WRL,
WRH
Write timing
Address
Data input
50ns.min
(0.5
tcyc-10)ns.min
td(BCLK-ALE)
td(BCLK-RD)
th(WR-CS)
Address
td(AD-ALE)
(0.5
tcyc-40)ns.min
(1.5
tcyc-50)ns.min
(0.5
tcyc-10)ns.min
td(BCLK-ALE)
(0.5
tcyc-40)ns.min
Address
40ns.max
tSU(DB-RD)
tac3(RD-DB)
(0.5
tcyc-10)ns.min
td(AD-RD)
0ns.min
tdZ(RD-AD)
8ns.max
td(AD-WR)
0ns.min
th(ALE-AD)
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage
: VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
(1.5
tcyc-60)ns.max
(0.5
tcyc-10)ns.min
(0.5
tcyc-10)ns.min
(0.5
tcyc-15)ns.min
VCC = 3.3 V
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