Rev.1.40
Oct 06, 2004
page 268 of 296
M306V7MG/MH/MJ-XXXFP, M306V7FG/FH/FJFP
7.2.3 Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed
by software commands. Operations must be executed from a memory other than the internal flash
memory, such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 031316 for USER area/031716 for OSD area) is
set to “1”, transition to CPU rewrite mode occurs and software commands can be accepted.
In the CPU rewrite mode, write to and read from software commands and data into even-numbered
address (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-num-
bered address. Commands are ignored with odd-numbered addresses.
Use software commands to control program and erase operations. Whether a program or erase opera-
tion has terminated normally or in error can be verified by reading the status register.
Figure 7.2.1 shows the flash memory control register and the flash memory switch register.
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Bit 0 of the flash memory control register is the RY/BY status flag used exclusively to read the operating
status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”.
Bit 1 of the flash memory control register is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode,
the CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area
other than the internal flash memory. To set this bit to “1”, it is necessary to write “0” and then write “1” in
succession. The bit can be set to “0” by only writing a “0” .
Bit 3 of the flash memory control register is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory
access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control
circuit. To release the reset, it is necessary to set this bit to “0”.
Bit 5 of the flash memory control register is a user ROM area select bit which is effective in only boot
mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to
the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note
that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be
accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of
whether the CPU rewrite mode is on or off. Use the control program except in the internal flash memory
to rewrite this bit.
The bit 1 of flash memory change register is a change bit of USER domain and OSD domain. An access
domain changes according to the contents of a setting of this bit. Access to the domain which is not
chosen cannot be performed including a memory lead. Moreover, after changing this bit before access of
an object domain is attained, the waiting time of 50 clock cycle is required.
Figure 7.2.2 shows a flowchart for setting/releasing the CPU rewrite mode. Always perform operation as
indicated in this flowchart.