Rev.1.00
May 18, 2004
page 163 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.14 Data Slicer
This microcomputer includes the data slicer function for the closed caption decoder (referred to as the
CCD) and video ID (referred to as the ID1). This function takes out CC and ID1 (note 2) superimposed in the
vertical blanking interval of a composite video signal. A composite video signal which makes the sync. tip’s
polarity negative is input to the CVIN pin.
When the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can
be cut off by setting bit 0 of the data slicer control register 1 (address 026016/030016) to “0.” These settings
can realize the low-power dissipation.
Notes 1. When using the data slicer, set bit 7 of the peripheral mode register (address 027D16) according
to the main clock frequency.
2. 525i/p:ID1 data slice can be performed. No CC data slice at 525p.
3. When there is no specification, it becomes the publication about 525i below.
Figure 2.14.1 Data slicer block diagram
1 1
0 000 00 00
0
1 0 10 00 00
00 0 00 00 0
10 0
Input amplitude = 1.75 Vpp
Composite video
signal
Note 1 (P164)
1 M
0.1
F
470
CVIN
2.2
F
1 k
200 pF
680 pF
HSYNC
HLF
Note 2 (P164)
Synchronizing
signal counter
Synchronizing
separation
circuit
Sync slice
circuit
Clamping
circuit
Low-pass
filter
Timing signal
generating
circuit
Clock run-in
determination
circuit
Data slice line
specification
circuit
Start bit detecting
circuit
ID1 reference
detection circuit
ID1 reference
judgment circuit
ID1 data clock
generating circuit
Data clock
generating circuit
Data register
control circuit
Address 026716
b1, b0
control circuit
Comparator 1
Comparator 2
+
–
+
–
Reference
voltage
generating
circuit
Internal absolute
standard voltage
generating
circuit
VHOLD
1000 pF
Data slicer control register 2
(address 026116/030116)
ID1 reserved register
(address 026116/030116)
(address 026016/030016)
(address 026916/030916)
(address 026616/030616)
Data slicer control register 1
Clock run-in detect
register
Caption position register
(address 026A16/030A16)
Data clock position register
Interrupt request
generating circuit
Data slicer
interrupt
request
Caption register 1
(addresses 026316 and 026216/
030316 and 030216)
(addresses 026516 and 026416/
030516 and 030416)
Data bus
Caption register 2
(addresses 026D16 and 030D16)
CRCC data register
(addresses 026816 and 030816)
Data slicer reserved register 1
(addresses 026E16)
Test reserved register 0
(addresses 030E16)
Test reserved register 1
(addresses 026F16 and 030F16)
Reserved register
External circuit
Note : Make the length of wiring which is
connected to VHOLD, HLF, and CVIN pin
as short as possible so that a leakage
current may not be generated when
mounting a resistor or
a capacitor on each pin.
Standard clock detection register
(addresses 026C16 and 030C16)
ID1 control register
(addresses 026B16 and 030B16)