參數(shù)資料
型號(hào)： M30810MC-XXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 8/85頁(yè)
文件大小： 876K
代理商： M30810MC-XXXFP
page 16
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1. Overview
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
P40 to P47
A16 to A22,
_____
A23
______
CS0 to CS3
MA8 to MA12
P50 to P57
CLKOUT
________
WRL
______
WR
_________
WRH
________
BHE
_____
RD
BCLK
__________
HLDA
__________
HOLD
ALE
________
RDY
______
DW
_________
CASL
_________
CASH
_______
RAS
P60 to P67
_________
CTS0, CTS1
_________
RTS0, RTS1
______
SS0, SS1
CLK0, CLK1
RxD0, RxD1
SCL0, SCL1
STxD0, STxD1
TxD0, TxD1
SDA0, SDA1
SRxD0, SRxD1
ISCLK2
OUTC21
I/O port P4
Address bus
Chip-select
Address bus
I/O port P5
Clock output
Bus control pin
DRAM bus control
pin
I/O port P6
UART pin
Intelligent I/O pin
I/O
O
I/O
O
I
O
I
O
I/O
I
O
I
I/O
I
I/O
O
I/O
I
I/O
O
8-bit I/O ports having equivalent functions to P0
______
Outputs 8 high-order address bits (A16 to A22, A23).
______
The highest-order bit (A23) inversed is also output.
_______
Outputs CS0 to CS3 signals. CS0 to CS3 are chip-select signals specifying an
external space.
Outputs row addresses and column addresses by time-sharing when accessing
the DRAM area.
8-bit I/O ports having equivalent functions to P0
Outputs the main clock divided by 8 or divided by 32 or the clock having the
same frequency as the sub clock from P53.
________
_________
______ ________
_____
_________
________
Outputs WRL, WRH, (WR, BHE), RD, BCLK, HLDA and ALE signals. WRL
_________
_______
______
and WRH or BHE and WR can be switched by program.
________
_________
_____
WRL, WRH and RD are selected
________
The WRL signal becomes "L" by writing data to an even address in an external
memory space.
_________
The WRH signal becomes "L" by writing data to an odd address in an external
memory space.
_____
The RD pin signal becomes "L" by reading data in an external memory space.
______ ________
_____
WR, BHE and RD are selected
______
The WR signal becomes "L" by writing data to an external memory space.
_____
The RD signal becomes "L" by reading data in an external memory space.
________
The BHE signal becomes "L" by accessing an odd address.
______ ________
_____
Select WR, BHE and RD for an external 8-bit data bus.
__________
While the HOLD pin is held "L", the microcomputer is placed in a hold state.
_________
In a hold state, HLDA outputs a "L" signal.
ALE is a signal latching the address.
________
While the RDY pin is held "L", the microcomputer is placed in a wait state.
______
The DW signal becomes "L" by writing data to the DRAM area.
_________
CASL and CASH are signals indicating a timing to latch column addresses.
_________
The CASL signal becomes "L" by accessing an even address.
__________
The CASH signal becomes "L" by accessing an odd address.
_______
RAS is a signal latching row addresses.
8-bit I/O ports having equivalent functions to P0
I/O pins for UART0 (P60 to P63) and UART1 (P64 to P67)
ISCKL2 inputs and outputs the clock for the intelligent I/O communication
function.
OUTC21 outputs the clock for the waveform generating function.
I : Input
O : Output
I/O : Input and output
Symbol
Function
I/O type
Description
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