參數(shù)資料
型號： M30812MC-XXXGP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)： 57/87頁
文件大?。?/td> 945K
代理商： M30812MC-XXXGP
page 58
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5. Electrical Characteristics (VCC=5V)
BCLK
ALE
18ns.max
-2ns.min
RD
18ns.max
-5ns.min
Hi-Z
DB
0ns.min
td(BCLK-ALE) th(BCLK-ALE)
td(BCLK-RD)
26ns.min(1)
tac2(RD-DB)(2)
CSi
td(BCLK-CS)
18ns.max(1)
ADi
18ns.max(1)
th(BCLK-AD)
-3ns.min
th(BCLK-CS)
-3ns.min
BHE
tcyc
td(BCLK-AD)
tac2(AD-DB)(2)
WR,WRL,
WRH
18ns.max
BCLK
CSi
18ns.max
ADi
18ns.max
-3ns.min
tcyc
BHE
DBi
td(BCLK-WR)
ALE
18ns.max
-2ns.min
Vcc=5V
th(BCLK-RD)
th(RD-DB)
tsu(DB-BCLK)
th(RD-CS)
0ns.min
td(BCLK-CS)
td(BCLK-AD)
td(BCLK-ALE)
th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)(1)
td(DB-WR)(1)
th(WR-DB)(1)
th(WR-AD)(1)
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
NOTES:
1. It varies with the operation frequency.
Measurement conditions
VCC=4.2 to 5.5V
Input high and low voltage:
VIH=2.5V, VIL=0
Output high and low voltage:
VOH=2.0V, VOL=0.8V
th(BCLK-ALE)
Read timing
Write timing (written in 2 cycles with no wait state)
Memory expansion mode and microprocessor mode (with a wait state)
th(RD-AD)
tw(WR)(1)
th(BCLK-WR)
0ns.min
Notes :
1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. It varies with the operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states.)
-3ns.min
Figure 5.3 VCC=5V Timing Diagram (2)
相關(guān)PDF資料
PDF描述
M3081LMC-XXXGP 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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