參數(shù)資料
型號： M3081LMC-XXXGP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 73/85頁
文件大小： 876K
代理商： M3081LMC-XXXGP
page 75
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5. Electrical Characteristics (VCC=3.3V)
BCLK
ALE
18ns.max
-2ns.min
RD
18ns.max
-3ns.min
Hi-Z
DB
0ns.min
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
30ns.min(1)
tac2(RD-DB)(2)
CSi
td(BCLK-CS)
18ns.max(1)
ADi
18ns.max(1)
th(BCLK-AD)
0ns.min
th(BCLK-CS)
0ns.min
BHE
tcyc
td(BCLK-AD)
tac2(AD-DB)(2)
WR,WRL,
WRH
18ns.max
0ns.min
BCLK
CSi
18ns.max
ADi
18ns.max
0ns.min
tcyc
BHE
DBi
td(BCLK-WR)
ALE
18ns.max
-2ns.min
Vcc=3.3V
th(BCLK-RD)
th(RD-DB)
th(RD-AD)
tsu(DB-BCLK)
th(RD-CS)
0ns.min
th(BCLK-WR)
td(BCLK-CS)
td(BCLK-AD)
td(BCLK-ALE)
th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)(1)
td(DB-WR)(1)
th(WR-DB)(1)
th(WR-AD)(1)
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 when 1 wait, n=2 with 2 wait states and n=3 with 3 wait states)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait
states)
NOTES:
1. It varies with the operation frequency.
Measurement conditions
VCC=3.0 to 3.6V
Input high and low voltage:
VIH=1.5V, VIL=0.5V
Output high and low voltage:
VOH=1.5V, VOL=1.5V
NOTES:
1. A value is guarantee with no external factor. Maximum 35ns is garanteed for td(BCLK-AD)+tsu(DB-BCLK).
2. It varies with the operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states)
th(BCLK-ALE)
Read timing
Write timing
Memory expansion mode and microprocessor mode (with a wait state)
tw(WR)(1)
Figure 5.11 VCC=3.3V Timing Diagram (2)
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