參數(shù)資料
型號: M3081LMC-XXXGP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 75/85頁
文件大小: 876K
代理商: M3081LMC-XXXGP
page 77
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5. Electrical Characteristics (VCC=3.3V)
BCLK
DW
DB
MAi
Vcc=3.3V
RAS
CASL
CASH
Hi-Z
tac4(CAS-DB)(2)
18ns.max(1)
th(BCLK-CAD)
0ns.min
tcyc
td(BCLK-RAD)
tac4(RAS-DB)(2)
Row address
Column address
th(BCLK-RAD)
0ns.min
18ns.max(1)
td(BCLK-CAD)
18ns.max(1)
td(BCLK-RAS)
18ns.max(1)
td(BCLK-CAS)
th(RAS-RAD)(1)
tRP(2)
tac4(CAD-DB)(2)
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
0ns.min
tsu(DB-BCLK)
30ns.min(1)
th(CAS-DB)
Measurement conditions
VCC=3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH=1.5V, VOL=1.5V
Read timing
Memory expansion mode and microprocessor mode
(With 2 wait states, when accessing the DRAM area)
NOTES:
1. A value is guaranteed with no external factor. Maximum 35ns is garanteed for the followings:
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
2. It varies with the operation frequency.
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Figure 5.13 VCC=3.3V Timing Diagram (4)
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