參數(shù)資料
型號(hào)： M30843FJGP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 69/91頁(yè)
文件大?。?/td> 903K
代理商： M30843FJGP
70
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to
change.
(3) Standard serial I/O Mode
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, pro-
gram, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires a purpose-specific pe-
ripheral unit.
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started by connecting “H” to the P41 (CE) pin
and “H” to the CNVSS pin (when VCC = 4.5 to 5.5 V, connect to
VCC, and when VCC = 3.0 to 4.5 V, apply 4.5 V to 5.5 V to Vpp
from an external source), and releasing the reset operation. (In the
ordinary microcomputer mode, set CNVss pin to “L” level.)
This control program is written in the Boot ROM area when the
product is shipped from Mitsubishi. Accordingly, make note of the
fact that the standard serial I/O mode cannot be used if the Boot
ROM area is rewritten in parallel I/O mode. Figure 69 shows the
pin connections for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four UART2
pins SCLK2, RxD2, TxD2 and SRDY2 (BUSY). The SCLK2 pin is the
transfer clock input pin through which an external transfer clock is
input. The TxD2 pin is for CMOS output. The SRDY2 (BUSY) pin
outputs “L” level when ready for reception and “H” level when re-
ception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 61 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
Outline Performance (Standard Serial I/O
Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O
(UART2).
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK2 pin, and are then input to the MCU via the RxD2 pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the TxD2 pin.
The TxD2 pin is for CMOS output. Transfer is in 8-bit units with
LSB first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY2 (BUSY) pin is “H” level. Accord-
ingly, always start the next transfer after the SRDY2 (BUSY) pin is
“L” level.
Also, data and status registers in a memory can be read after in-
putting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
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