參數(shù)資料
型號: M30843FJGP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 72/91頁
文件大?。?/td> 903K
代理商: M30843FJGP
73
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to
change.
Fig. 72 Timing for clear status register
qClear Status Register Command
This command clears the bits (SR3 to SR5) which are set when
the status register operation ends in error. When the “5016” com-
mand code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY2
(BUSY) signal changes from “H” to “L” level.
qPage Program Command
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page pro-
gram command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
(3) From the 4th byte onward, as write data (D0 to D7) for the page
(256 bytes) specified with addresses A8 to A23 is input se-
quentially from the smallest address first, that page is
automatically written.
When reception setup for the next 256 bytes ends, the SRDY2
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
Fig. 73 Timing for page program
5016
SCLK2
RxD2
TxD2
SRDY2(BUSY)
4116
A8 to A15 A16 to A23
data0
data255
SCLK2
RxD2
TxD2
SRDY2(BUSY)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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