參數(shù)資料
型號: M30L0R8000B0
廠商: 意法半導體
英文描述: 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
中文描述: 256兆位(16Mb的x16插槽,多銀行,多層次,多突發(fā))1.8V電源快閃記憶體
文件頁數(shù): 29/83頁
文件大小: 1363K
代理商: M30L0R8000B0
29/83
M30L0R8000T0, M30L0R8000B0
Table 11. Configuration Register
Note: 1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported.
Bit
Description
Value
Description
CR15
Read Select
0
Synchronous Read
1
Asynchronous Read (Default at power-on)
CR14
Reserved
CR13-CR11
X-Latency
010
2 clock latency
(1)
011
3 clock latency
100
4 clock latency
101
5 clock latency
110
6 clock latency
111
7 clock latency (default)
Other configurations reserved
CR10
Wait Polarity
0
WAIT is active Low
1
WAIT is active high (default)
CR9
Data Output
Configuration
0
Data held for one clock cycle
1
Data held for two clock cycles (default)
1
CR8
Wait Configuration
0
WAIT is active during WAIT state
1
WAIT is active one data cycle before WAIT state (default)
1
CR7
Burst Type
0
Reserved
1
Sequential (default)
CR6
Valid Clock Edge
0
Falling Clock edge
1
Rising Clock edge (default)
CR5-CR4
Reserved
CR3
Wrap Burst
0
Wrap
1
No Wrap (default)
CR2-CR0
Burst Length
001
4 Words
010
8 Words
011
16 Words
111
Continuous (default)
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