參數(shù)資料
型號(hào): M30LW128D110ZA6T
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product
中文描述: 128兆位(兩個(gè)64兆比特,x8/x16,統(tǒng)一座,快閃記憶體)3V電源,多記憶體產(chǎn)品
文件頁數(shù): 31/57頁
文件大?。?/td> 860K
代理商: M30LW128D110ZA6T
31/57
M30LW128D
Figure 11. Bus Read AC Waveforms
Note: 1. Refer to Table 3 for details of how the device is enabled.
2. BYTE can be Low or High. The BYTE signal is not available with the LFBGA88 package.
Table 16. Bus Read AC Characteristics
Symbol
Parameter
Test Condition
M30LW128D
Unit
110
t
AVAV
Address Valid to Address Valid
E = V
IL
, G = V
IL
Min
110
ns
t
AVQV
Address Valid to Output Valid
E = V
IL
, G = V
IL
Max
110
ns
t
AXQX
Address Transition to Output Transition
E = V
IL
, G = V
IL
Min
0
ns
t
BLQV
Byte Low (or High) to Output Valid
E = V
IL
, G = V
IL
Max
1
μs
t
BLQZ
Byte Low (or High) to Output Hi-Z
E = V
IL
, G = V
IL
Max
1
μs
t
EHQX
Chip Enable High to Output Transition
G = V
IL
Min
0
ns
t
EHQZ
Chip Enable High to Output Hi-Z
G = V
IL
Max
25
ns
t
ELBL
Chip Enable Low to Byte Low (or High)
G = V
IL
Max
10
ns
t
ELQX
Chip Enable Low to Output Transition
G = V
IL
Min
0
ns
t
ELQV
Chip Enable Low to Output Valid
G = V
IL
Max
110
ns
t
GHQX
Output Enable High to Output Transition
E = V
IL
Min
0
ns
t
GHQZ
Output Enable High to Output Hi-Z
E = V
IL
Max
15
ns
t
GLQX
Output Enable Low to Output Transition
E = V
IL
Min
0
ns
t
GLQV
Output Enable Low to Output Valid
E = V
IL
Max
25
ns
AI07509
E
(1)
G
A0-A23
DQ0-DQ15
VALID
tAXQX
tELQX
tAVQV
tGLQV
tEHQZ
tGHQX
OUTPUT
tAVAV
tEHQX
tGHQZ
tGLQX
tELQV
BYTE
(2)
tELBL
tBLQV
tBLQZ
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