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參數(shù)資料
| 型號： | M30LW128D110ZA6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
| 中文描述： | 128兆位（兩個64兆比特，x8/x16，統(tǒng)一座，快閃記憶體）3V電源，多記憶體產(chǎn)品 |
| 文件頁數(shù)： | 45/57頁 |
| 文件大?。?/td> | 860K |
| 代理商： | M30LW128D110ZA6T |
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M30LW128D
Table 31. Extended Query information
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
2. In x8 mode, A0 must be set to V
IL
, otherwise 00h will be output.
Address
Data (Hex)
Description
offset
x16
x8
(2)
(P)h
0031h
62h
50h
"P"
Query ASCII string - Extended Table
(P+1)h
0032h
64h
52h
"R"
(P+2)h
0033h
66h
49h
"I"
(P+3)h
0034h
68h
31h
Major version number
(P+4)h
0035h
6Ah
31h
Minor version number
(P+5)h
0036h
6Ch
CEh
Optional Feature: (1=yes, 0=no)
bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Protect/Unprotect Supported (1=yes)
bit4, Queue Erase Supported (0=no)
bit5, Instant Individual Block locking (0=no)
bit6, Protection bits supported (1=yes)
bit7, Page Read supported (1=yes)
bit8, Synchronous Read supported (0=no)
bit9, Multi chip device (1=yes)
bit10, Simultaneous operations supported (1=yes)
Bits 11 to 31 reserved for future use
(P+6)h
0037h
6Eh
06h
(P+7)h
0038h
70h
00h
(P+8)h
0039h
72h
00h
(P+9)h
003Ah
74h
01h
Function allowed after Suspend:
Program allowed after Erase Suspend (1=yes)
Bits 1 to 7 reserved for future use
(P+A)h
003Bh
76h
01h
Block Status Register
bit0, Block Protect-Bit status active (1=yes)
bit1, Block Lock-Down Bit status (not available)
bits 2 to 15 reserved for future use
(P+B)h
003Ch
78h
00h
(P+C)h
003Dh
7Ah
33h
V
DD
OPTIMUM Program/Erase voltage conditions
(P+D)h
003Eh
7Ch
00h
V
PP
OPTIMUM Program/Erase voltage conditions
(P+E)h
003Fh
7Eh
01h
OTP protection: No. of protection register fields
(P+F)h
0040h
80h
80h
Protection Register’s start address, least significant bits
(P+10)h
0041h
82h
00h
Protection Register’s start address, most significant bits
(P+11)h
0042h
84h
03h
n where 2
n
is number of factory reprogrammed bytes
(P+12)h
0043h
86h
03h
n where 2
n
is number of user programmable bytes
(P+13)h
0044h
88h
03h
Page Read: 2
n
Bytes (n = bits 0-7)
(P+14)h
0045h
8Ah
00h
Synchronous mode configuration fields
(P+15)h
0046h
8Ch
Reserved for future use
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