參數(shù)資料
型號(hào)： M32000D4AFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE CHIP 32 BIT CMOS MICROCOMPUTER
中文描述： 單芯片32位CMOS微機(jī)
文件頁(yè)數(shù)： 7/45頁(yè)
文件大小： 535K
代理商： M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
7
PIN DESCRIPTION (2/3)
type
bus
control
pin name
SID
name
space
identifier
I/O
output
(Hi-z)*
function
Space identifier between user space and I/O space.
SID = "L": user space
SID = "H": I/O space
SID = undefined: when idle
____
to the LSB side (D8 to D15). During a read bus cycle, both BCH
____
and BCL are an "L" level.
During a write bus cycle, either BCH and/or BCL is an "L" level
depending on the byte(s) to be written.
When accessing the internal DRAM from an external bus master,
the byte control signal is input from the system bus side.
When the M32000D4AFP drives an external bus cycle, BS goes
to an "L" level at the start of the bus cycle.
__
In burst transfer, BS goes to the "L" level for each transfer
cycle. When accessing internal resources such as an internal
__
DRAM or internal I/O register, BS is not output.
Indicates whether the bus cycle that the M32000D4AFP drives is
an instruction fetch access cycle or an operand access cycle.
ST = "L": for instruction fetch access
ST = "H": for operand access
ST = undefined: when idle
Outputs R/W to identify whether the external bus cycle a read or
a write cycle. When accessing the internal DRAM from an external
__
bus master, R/W is input from the external bus.
The M32000D4AFP drives two consecutive bus cycles to access
32-bit data allocated on the 32-bit word boundary.
For instruction fetches, it drives 8 (max.) consecutive cycles
(8 cycles in instruction cache mode) to data on the 128-bit boundary.
During these consecutive bus cycles, BURST goes to "L" level.
When accessing 32-bit data, an "L" level followed by an "H" level
is output from address A30, because the MSB-side 16 bits are
accessed prior to the LSB-side 16 bits.
When accessing 128-bit data, the addresses are output from an
arbitrary 16-bit aligned address and wraparound within a 128-bit
aligned boundary.
____
____
byte control
I/O
(Hi-z)*
____
BS
bus start
output
(Hi-z)*
ST
bus status
output
(Hi-z)*
__
R/W
read/write
I/O
(Hi-z)*
BURST
burst
output
(Hi-z)*
* (Hi-z): This pin goes to high-impedance in the hold state.
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