參數(shù)資料
型號: M34501M4
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機的CMOS
文件頁數(shù): 18/113頁
文件大?。?/td> 1252K
代理商: M34501M4
18
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as fol-
lows (Figure 14).
Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
Interrupt enable flag (INTE)
INTE flag is cleared to
0
so that interrupts are disabled.
Interrupt request flag
Only the request flag for the current interrupt source is cleared to
0.
Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is ex-
ecuted after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an in-
terrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Fig. 13 Program example of interrupt processing
Program counter (PC)
............................................................... Each interrupt address
Stack register (SK)
.............................................The address of main routine to be
executed when returning
Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
Interrupt request flag (only the flag for the current interrupt
source)................................................................................... 0
Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 15 Interrupt system diagram
Fig. 14 Internal state when interrupt occurs
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Address 6
in page 1
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Timer 2
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Completion of
A-D conversion
Address C
in page 1
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