–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V1
0
= 0: (EXF0) = 1
(INT) = “L”
However, I1
2
= 0
(INT) = “H”
However, I1
2
= 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V1
2
= 0: (T1F) = 1
V1
3
= 0: (T2F) =1
Skip condition
Datailed description
C
95
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
When V1
0
= 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,
clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.
When V1
0
= 1 : This instruction is equivalent to the NOP instruction.
(V1
0
: bit 0 of interrupt control register
V1)
When I1
2
= 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when
the level of INT pin is “H.”
When I1
2
= 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when
the level of INT pin is “L.” (I1
2
: bit 2 of interrupt control register I1)
Transfers the contents of interrupt control register V1 to register A.
Transfers the contents of register A to interrupt control register V1.
Transfers the contents of interrupt control register V2 to register A.
Transfers the contents of register A to interrupt control register V2.
Transfers the contents of interrupt control register I1 to register A.
Transfers the contents of register A to interrupt control register I1.
Transfers the contents of timer control register W1 to register A.
Transfers the contents of register A to timer control register W1.
Transfers the contents of timer control register W2 to register A.
Transfers the contents of register A to timer control register W2.
Transfers the contents of timer control register W6 to register A.
Transfers the contents of register A to timer control register W6.
Transfers the high-order 4 bits (T1
7
–T1
4
) of timer 1 to register B.
Transfers the low-order 4 bits (T1
3
–T1
0
) of timer 1 to register A.
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Trans-
fers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
Transfers the high-order 4 bits (T2
7
–T2
4
) of timer 2 to register B.
Transfers the low-order 4 bits (T2
3
–T2
0
) of timer 2 to register A.
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Trans-
fers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
Transfers the contents of register B to the high-order 4 bits (R1
7
–R1
4
) of reload register R1, and the con-
tents of register A to the low-order 4 bits (R1
3
–R1
0
) of reload register R1.
When V1
2
= 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping,
clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction.
When V1
2
= 1 : This instruction is equivalent to the NOP instruction.
(V1
2
: bit 2 of interrupt control register V1)
When V1
3
= 0 : Skips the next instruction when timer 1 interrupt request flag T2F is “1.” After skipping,
clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction.
When V1
3
= 1 : This instruction is equivalent to the NOP instruction.
(V1
3
: bit 3 of interrupt control register V1)