參數(shù)資料
型號： M34509G4H-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 83/145頁
文件大小： 1060K
代理商： M34509G4H-XXXFP
Rev.1.03
2009.07.27
page 40 of 140
REJ03B0147-0103
4509 Group
Table 13 Change of successive comparison register AD during A/D conversion
Comparison voltage (Vref) value
Change of successive comparison register AD
At starting conversion
±
1: 1st comparison result
3: 3rd comparison result
9: 9th comparison result
2: 2nd comparison result
8: 8th comparison result
A: 10th comparison result
1st comparison
2nd comparison
3rd comparison
After 10th comparison
completes
1
-----
0
1
2
0
1
3
0
8
0
9
0
A
A/D conversion result
VDD
2
VDD
2
VDD
2
VDD
2
VDD
4
VDD
4
VDD
8
VDD
1024
○○○
○
-------------
Fig. 33 Setting registers
A/D control register Q1
AIN0 pin selected
A/D conversion mode
0
000
(Bit 3)
(Bit 0)
(7) A/D conversion timing chart
Figure 32 shows the A/D conversion timing chart.
Fig. 32 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P20/AIN0 pin is A/D converted, and the high-or-
der 4 bits of the converted data are stored in address M(Z, X, Y) =
(0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and
the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/
D interrupt is not used in this example.
Select the AIN0 pin function and A/D conversion mode with the
register Q1 (refer to Figure 33).
Execute the ADST instruction and start A/D conversion.
Examine the state of ADF flag with the SNZAD instruction to de-
termine the end of A/D conversion.
Transfer the low-order 2 bits of converted data to the high-order 2
bits of register A (TALA instruction).
Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
Transfer the high-order 8 bits of converted data to registers A and
B (TABAD instruction).
Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
ADST instruction
A/D conversion
completion flag (ADF)
62 machine cycles
DAC operation signal
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