參數(shù)資料
型號: M34551M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù): 44/71頁
文件大?。?/td> 966K
代理商: M34551M4-XXXFP
Skip condition
Detailed description
Carry
flag
CY
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
(Y) = 15
(Y) = 0
Continuous
description
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
and other LA instructions coded continuously are skipped.
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, 1 stage of stack register is used.
46
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